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PRELIMINARY
Integrated Circuit Systems, Inc.
ICS843071I
FEMTOCLOCKSTM CRYSTAL-TO- LVPECL CLOCK GENERATOR
FEATURES
* (1) Differential LVPECL output * Crystal oscillator interface, 18pF parallel resonant crystal (20.833MHz - 28.3MHz) * Output frequency range: 62.5MHz - 170MHz * VCO range: 500MHz - 680MHz * RMS phase jitter @ 150MHz, using a 25MHz crystal (12KHz - 20MHz): 0.67ps (typical) * 3.3V or 2.5V operating supply * -40C to 85C ambient operating temperature
GENERAL DESCRIPTION
The ICS843071I is a Serial ATA (SATA)/Serial Attached SCSI (SAS) Clock Generator and a HiPerClockSTM member of the HiPerClocks TM family of high performance devices from ICS. The ICS843071I uses an 18pF parallel resonant crystal over the range of 20.833MHz - 28.3MHz. For SATA/SAS applications, a 25MHz crystal is used and either 75MHz or 150MHz may be selected with the FREQ_SEL pin. The ICS843071I has excellent <1ps phase jitter performance, over the 12KHz 20MHz integration range. The ICS843071I is packaged in a small 8-pin TSSOP, making it ideal for use in systems with limited board space.
ICS
COMMON CONFIGURATION TABLE - SERIAL ATA/SERIAL ATTACHED SCSI
Inputs Crystal Frequency (MHz) 25 25 FREQ_SEL 0 1 M 24 24 N 4 8 Multiplication Value M/N 6 3 Output Frequency (MHz) 150 75
BLOCK DIAGRAM
FREQ_SEL Pullup
PIN ASSIGNMENT
FREQ_SEL N 0 /4 1 /8
VCCA XTAL_OUT XTAL_IN VEE 1 2 3 4 8 7 6 5 VCC Q0 nQ0 FREQ_SEL
XTAL_IN
OSC
XTAL_OUT
Phase Detector
VCO
500MHz - 680MHz
Q0 nQ0
ICS843071I
8-Lead TSSOP 4.40mm x 3.0mm x 0.925mm package body G Package Top View
M = /24 (fixed)
The Preliminary Information presented herein represents a product in prototyping or pre-production. The noted characteristics are based on initial product characterization. Integrated Circuit Systems, Incorporated (ICS) reserves the right to change any circuitry or specifications without notice. 843071AGI www.icst.com/products/hiperclocks.html REV. A MARCH 11, 2005
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PRELIMINARY
Integrated Circuit Systems, Inc.
ICS843071I
FEMTOCLOCKSTM CRYSTAL-TO- LVPECL CLOCK GENERATOR
Type Power Input Power Input Pullup Description Analog supply pin. Crystal oscillator interface. XTAL_IN is the input, XTAL_OUT is the output. Negative supply pin. Frequency select pin. LVCMOS/LVTTL interface levels. Differential clock outputs. LVPECL interface levels. Core supply pin.
TABLE 1. PIN DESCRIPTIONS
Number 1 2, 3 4 5 6, 7 8 Name VCCA XTAL_OUT, XTAL_IN VEE FREQ_SEL nQ0, Q0 VCC
Output Power
NOTE: Pullup refers to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol CIN RPULLUP Parameter Input Capacitance Input Pullup Resistor Test Conditions Minimum Typical 4 51 Maximum Units pF k
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PRELIMINARY
Integrated Circuit Systems, Inc.
ICS843071I
FEMTOCLOCKSTM CRYSTAL-TO- LVPECL CLOCK GENERATOR
4.6V -0.5V to VCC + 0.5 V 10mA 15mA 101.7C/W (0 mps) -65C to 150C NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, VDD Inputs, VI Outputs, IO (LVDS) Continuous Current Surge Current Package Thermal Impedance, JA Storage Temperature, TSTG
TABLE 3A. POWER SUPPLY DC CHARACTERISTICS, VCC = VCCA = 3.3V5%, TA = -40C TO 85C
Symbol VCC VCCA IEE ICCA Parameter Core Supply Voltage Analog Supply Voltage Power Supply Current Analog Supply Current Test Conditions Minimum 3.135 3.135 Typical 3.3 3.3 58 7 Maximum 3.465 3.465 Units V V mA mA
TABLE 3B. POWER SUPPLY DC CHARACTERISTICS, VCC = VCCA = 2.5V5%, TA = -40C TO 85C
Symbol VCC VCCA IEE ICCA Parameter Core Supply Voltage Analog Supply Voltage Power Supply Current Analog Supply Current Test Conditions Minimum 2.375 2.375 Typical 2.5 2.5 55 7 Maximum 2.625 2.625 Units V V mA mA
TABLE 3C. LVCMOS/LVTTL DC CHARACTERISTICS, VCC = VCCA = 3.3V5% OR 2.5V5%, TA = -40C TO 85C
Symbol VIH VIL IIH IIL Parameter Input High Voltage Input Low Voltage Input High Current Input Low Current FREQ_SEL FREQ_SEL Test Conditions 3.3V 2.5V 3.3V 2.5V VCC = VIN = 3.465V or 2.625V VCC = 3.465V or 2.625V, VIN = 0V -150 Minimum 2 1.7 -0.3 -0.3 Typical Maximum VCC + 0.3 VCC + 0.3 0.8 0.7 5 Units V V V V A A
NOTE 1: Outputs terminated with 50 to VCC/2. See Parameter Measurement Information Section, "Output Load Test Circuit" diagrams.
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PRELIMINARY
Integrated Circuit Systems, Inc.
ICS843071I
FEMTOCLOCKSTM CRYSTAL-TO- LVPECL CLOCK GENERATOR
Test Conditions Minimum VCC - 1.4 VCC - 2.0 0.6 Typical Maximum VCC - 0.9 VCC - 1.7 1.0 Units V V V
TABLE 3D. LVPECL DC CHARACTERISTICS, VCC = VCC = 3.3V5% OR 2.5V5%, TA = -40C TO 85C
Symbol VOH VOL VSWING Parameter Output High Voltage; NOTE 1 Output Low Voltage; NOTE 1 Peak-to-Peak Output Voltage Swing
NOTE 1: Outputs terminated with 50 to VCC - 2V.
TABLE 4. CRYSTAL CHARACTERISTICS
Parameter Mode of Oscillation Frequency Equivalent Series Resistance (ESR) Shunt Capacitance 20.833 Test Conditions Minimum Typical Fundamental 28.3 50 7 MHz pF Maximum Units
TABLE 5A. AC CHARACTERISTICS, VCC = VCCA = 3.3V5%, TA = -40C TO 85C
Symbol fOUT Parameter Output Frequency RMS Phase Jitter ( Random); NOTE 1 Output Rise/Fall Time 150MHz @ Integration Range: 12KHz - 20MHz 75MHz @ Integration Range: 12KHz - 20MHz 20% to 80% Test Conditions Minimum 62.5 0.67 0.60 350 50 Typical Maximum 170 Units MHz ps ps ps %
tjit(O)
tR / tF
odc Output Duty Cycle NOTE 1: Please refer to the Phase Noise Plots following this section.
TABLE 5B. AC CHARACTERISTICS, VCC = VCCA = 2.5V5%, TA = -40C TO 85C
Symbol fOUT Parameter Output Frequency RMS Phase Jitter ( Random); NOTE 1 Output Rise/Fall Time 150MHz @ Integration Range: 12KHz - 20MHz 75MHz @ Integration Range: 12KHz - 20MHz 20% to 80% Test Conditions Minimum 62.5 0.78 0.75 350 50 Typical Maximum 170 Units MHz ps ps ps %
tjit(O)
t R / tF
odc Output Duty Cycle NOTE 1: Please refer to the Phase Noise Plots following this section.
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PRELIMINARY
Integrated Circuit Systems, Inc.
ICS843071I
FEMTOCLOCKSTM CRYSTAL-TO- LVPECL CLOCK GENERATOR
TYPICAL PHASE NOISE AT 75MHZ
0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130 -140 -150 -160 -170 -180 -190 10 100 1k
Filter 75MHz
RMS Phase Noise Jitter 12KHz to 20MHz = 0.60ps (typical)
NOISE POWER dBc Hz
Raw Phase Noise Data
Phase Noise Result by adding a Filter to raw data
10k 100k 1M 10M 100M
TYPICAL PHASE NOISE AT 150MHZ
0 -10 -20 -30 -40 -50 -60 -70 -80 -90
Filter 150MHz
RMS Phase Noise Jitter 12KHz to 20MHz = 0.67ps (typical)
OFFSET FREQUENCY (HZ)
NOISE POWER dBc Hz
Raw Phase Noise Data
-100 -110 -120 -130 -140 -150 -160 -170 -180 -190 10 100
Phase Noise Result by adding a Filter to raw data
1k 10k
100k
1M
10M
100M
OFFSET FREQUENCY (HZ)
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PRELIMINARY
Integrated Circuit Systems, Inc.
ICS843071I
FEMTOCLOCKSTM CRYSTAL-TO- LVPECL CLOCK GENERATOR
PARAMETER MEASUREMENT INFORMATION
2V 2V
V CC
Qx
SCOPE
V CC
Qx
SCOPE
LVPECL
nQx
LVPECL
nQx
VEE
VEE
-1.3V 0.165V
-0.5V 0.125V
LVPECL 3.3V OUTPUT LOAD AC TEST CIRCUIT
LVPECL 2.5V OUTPUT LOAD AC TEST CIRCUIT
nQ0 80% Clock Outputs 80% VSW I N G 20% tR tF
odc = t PW t PERIOD
Q0
Pulse Width t
PERIOD
20%
OUTPUT RISE/FALL TIME
OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD
Phase Noise Plot
Noise Power
Phase Noise Mask
f1
Offset Frequency
f2
RMS Jitter = Area Under the Masked Phase Noise Plot
RMS PHASE JITTER
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PRELIMINARY
Integrated Circuit Systems, Inc.
ICS843071I
FEMTOCLOCKSTM CRYSTAL-TO- LVPECL CLOCK GENERATOR APPLICATION INFORMATION
POWER SUPPLY FILTERING TECHNIQUES
As in any high speed analog circuitry, the power supply pins are vulnerable to random noise. The ICS843071I provides separate power supplies to isolate any high switching noise from the outputs to the internal PLL. VCC and VCCA should be individually connected to the power supply plane through vias, and bypass capacitors should be used for each pin. To achieve optimum jitter performance, power supply isolation is required. Figure 1 illustrates how a 10 resistor along with a 10F and a .01F bypass capacitor should be connected to each VCCA pin.
3.3V or 2.5V VCC .01F V CCA .01F 10F 10
FIGURE 1. POWER SUPPLY FILTERING
TERMINATION
FOR
2.5V LVPECL OUTPUT
ground level. The R3 in Figure 2B can be eliminated and the termination is shown in Figure 2C.
Figure 2A and Figure 2B show examples of termination for 2.5V LVPECL driver. These terminations are equivalent to terminating 50 to VCC - 2V. For VCC = 2.5V, the VCC - 2V is very close to
2.5V 2.5V VCC=2.5V R1 250 Zo = 50 Ohm + Zo = 50 Ohm 2,5V LVPECL Driv er R2 62.5 R4 62.5 R3 250
2.5V VCC=2.5V Zo = 50 Ohm + Zo = 50 Ohm 2,5V LVPECL Driv er R1 50 R2 50
R3 18
FIGURE 2A. 2.5V LVPECL DRIVER TERMINATION EXAMPLE
FIGURE 2B. 2.5V LVPECL DRIVER TERMINATION EXAMPLE
2.5V VCC=2.5V Zo = 50 Ohm + Zo = 50 Ohm 2,5V LVPECL Driv er R1 50 R2 50
FIGURE 2C. 2.5V LVPECL TERMINATION EXAMPLE
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PRELIMINARY
Integrated Circuit Systems, Inc.
ICS843071I
FEMTOCLOCKSTM CRYSTAL-TO- LVPECL CLOCK GENERATOR
drive 50 transmission lines. Matched impedance techniques should be used to maximize operating frequency and minimize signal distortion. Figures 3A and 3B show two different layouts which are recommended only as guidelines. Other suitable clock layouts may exist and it would be recommended that the board designers simulate to guarantee compatibility across all printed circuit and clock component process variations.
TERMINATION FOR 3.3V LVPECL OUTPUT
The clock layout topology shown below is a typical termination for LVPECL outputs. The two different layouts mentioned are recommended only as guidelines. FOUT and nFOUT are low impedance follower outputs that generate ECL/LVPECL compatible outputs. Therefore, terminating resistors (DC current path to ground) or current sources must be used for functionality. These outputs are designed to
3.3V
Zo = 50 FOUT FIN
125 Zo = 50 FOUT
50 50 VCC - 2V RTT
125
Zo = 50
FIN
Zo = 50 84 84
RTT =
1 Zo (VOH + VOL / VCC - 2) - 2
FIGURE 3A. LVPECL OUTPUT TERMINATION
FIGURE 3B. LVPECL OUTPUT TERMINATION
CRYSTAL INPUT INTERFACE
The ICS843071I has been characterized with 18pF parallel resonant crystals. The capacitor values, C1 and C2, shown in Figure 4 below were determined using a 25MHz, 18pF parallel resonant crystal and were chosen to minimize the ppm error. The optimum C1 and C2 values can be slightly adjusted for different board layouts.
XTAL_IN C1 22p X1 18pF Parallel Cry stal XTAL_OUT C2 22p ICS84332 ICS843071I
Figure 4. CRYSTAL INPUt INTERFACE
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PRELIMINARY
Integrated Circuit Systems, Inc.
ICS843071I
FEMTOCLOCKSTM CRYSTAL-TO- LVPECL CLOCK GENERATOR POWER CONSIDERATIONS
This section provides information on power dissipation and junction temperature for the ICS843071I. Equations and example calculations are also provided.
1. Power Dissipation. The total power dissipation for the ICS843071I is the sum of the core power plus the power dissipated in the load(s). The following is the power dissipation for VCC = 3.3V + 5% = 3.465V, which gives worst case results. NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
* *
Power (core)MAX = VCC_MAX * IEE_TYP = 3.465V * 58mA = 200.97mW Power (outputs)MAX = 30mW/Loaded Output pair
Total Power_MAX (3.465V, with all outputs switching) = 200.97mW + 30mW = 230.97mW
2. Junction Temperature. Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device. The maximum recommended junction temperature for HiPerClockSTM devices is 125C.
The equation for Tj is as follows: Tj = JA * Pd_total + TA Tj = Junction Temperature JA = Junction-to-Ambient Thermal Resistance Pd_total = Total Device Power Dissipation (example calculation is in section 1 above) TA = Ambient Temperature In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance JA must be used. Assuming a moderate air flow of 1 meter per second and a multi-layer board, the appropriate value is 90.5C/W per Table 6 below. Therefore, Tj for an ambient temperature of 85C with all outputs switching is: 85C + 0.231W * 90.5C/W = 106C. This is well below the limit of 125C. This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow, and the type of board (single layer or multi-layer).
TABLE 6. THERMAL RESISTANCE JA
FOR
8-PIN TSSOP, FORCED CONVECTION
JA by Velocity (Meters per Second)
0
Multi-Layer PCB, JEDEC Standard Test Boards 101.7C/W
1
90.5C/W
2.5
89.8C/W
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PRELIMINARY
Integrated Circuit Systems, Inc.
ICS843071I
FEMTOCLOCKSTM CRYSTAL-TO- LVPECL CLOCK GENERATOR
3. Calculations and Equations. The purpose of this section is to derive the power dissipated into the load. LVPECL output driver circuit and termination are shown in Figure 5.
VCC
Q1
VOUT RL 50 VCC - 2V
FIGURE 5. LVPECL DRIVER CIRCUIT
AND
TERMINATION
To calculate worst case power dissipation into the load, use the following equations which assume a 50 load, and a termination voltage of V - 2V.
CC
*
For logic high, VOUT = V (V
CCO_MAX
OH_MAX
=V
CC_MAX
- 0.9V
-V
OH_MAX
) = 0.9V =V - 1.7V
*
For logic low, VOUT = V (V
CCO_MAX
OL_MAX
CC_MAX
-V
OL_MAX
) = 1.7V
Pd_H is power dissipation when the output drives high. Pd_L is the power dissipation when the output drives low. Pd_H = [(V
OH_MAX
- (V
CC_MAX
- 2V))/R ] * (V
L
CC_MAX
-V
OH_MAX
) = [(2V - (V
CC_MAX
-V
OH_MAX
))/R ] * (V
L
CC_MAX
-V
OH_MAX
)=
[(2V - 0.9V)/50] * 0.9V = 19.8mW
Pd_L = [(V
OL_MAX
- (V
CC_MAX
- 2V))/R ] * (V
L
CC_MAX
-V
OL_MAX
) = [(2V - (V
CC_MAX
-V
OL_MAX
))/R ] * (V
L
CC_MAX
-V
OL_MAX
)=
[(2V - 1.7V)/50] * 1.7V = 10.2mW Total Power Dissipation per output pair = Pd_H + Pd_L = 30mW
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PRELIMINARY
Integrated Circuit Systems, Inc.
ICS843071I
FEMTOCLOCKSTM CRYSTAL-TO- LVPECL CLOCK GENERATOR RELIABILITY INFORMATION
TABLE 7.
JAVS. AIR FLOW TABLE FOR 8 LEAD TSSOP
JA by Velocity (Linear Feet per Minute)
0 1
90.5C/W
2.5
89.8C/W
Multi-Layer PCB, JEDEC Standard Test Boards
101.7C/W
TRANSISTOR COUNT
The transistor count for ICS843071I is: 1732
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PRELIMINARY
Integrated Circuit Systems, Inc.
ICS843071I
FEMTOCLOCKSTM CRYSTAL-TO- LVPECL CLOCK GENERATOR
8 LEAD TSSOP
PACKAGE OUTLINE - G SUFFIX
FOR
TABLE 8. PACKAGE DIMENSIONS
SYMBOL N A A1 A2 b c D E E1 e L aaa 0.45 0 -4.30 0.65 BASIC 0.75 8 0.10 -0.05 0.80 0.19 0.09 2.90 6.40 BASIC 4.50 Millimeters Minimum 8 1.20 0.15 1.05 0.30 0.20 3.10 Maximum
Reference Document: JEDEC Publication 95, MO-153
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PRELIMINARY
Integrated Circuit Systems, Inc.
ICS843071I
FEMTOCLOCKSTM CRYSTAL-TO- LVPECL CLOCK GENERATOR
Marking 3071A 3071A Package 8 Lead TSSOP 8 Lead TSSOP Shipping Packaging tube 2500 tape & reel Temperature -40C to 85C -40C to 85C
TABLE 9. ORDERING INFORMATION
Part/Order Number ICS843071AGI ICS843071AGIT
The aforementioned trademarks, HiPerClockSTM and FemtoClocksTM are a trademark of Integrated Circuit Systems, Inc. or its subsidiaries in the United States and/or other countries. While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial and industrial applications. Any other applications such as those requiring high reliability or other extraordinary environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or critical medical instruments. 843071AGI
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